diff --git a/board/freescale/ls1046afrwy/Kconfig b/board/freescale/ls1046afrwy/Kconfig
new file mode 100644
index 0000000..6a4c3e9
--- /dev/null
+++ b/board/freescale/ls1046afrwy/Kconfig
@@ -0,0 +1,17 @@
+
+if TARGET_LS1046AFRWY
+
+config SYS_BOARD
+	default "ls1046afrwy"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls1046afrwy"
+
+source "board/freescale/common/Kconfig"
+endif
diff --git a/board/freescale/ls1046afrwy/MAINTAINERS b/board/freescale/ls1046afrwy/MAINTAINERS
new file mode 100644
index 0000000..357d23e
--- /dev/null
+++ b/board/freescale/ls1046afrwy/MAINTAINERS
@@ -0,0 +1,7 @@
+LS1046AFRWY BOARD
+M:	Pramod Kumar <pramod.kumar_1@nxp.com>
+S:	Maintained
+F:	board/freescale/ls1046afrwy/
+F:	board/freescale/ls1046afrwy/ls1046afrwy.c
+F:	include/configs/ls1046afrwy.h
+F:	configs/ls1046afrwy_tfa_defconfig
diff --git a/board/freescale/ls1046afrwy/Makefile b/board/freescale/ls1046afrwy/Makefile
new file mode 100644
index 0000000..c70f5cd
--- /dev/null
+++ b/board/freescale/ls1046afrwy/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2019 NXP
+
+obj-y += ddr.o
+obj-y += ls1046afrwy.o
+obj-$(CONFIG_NET) += eth.o
diff --git a/board/freescale/ls1046afrwy/README b/board/freescale/ls1046afrwy/README
new file mode 100644
index 0000000..d7b5a77
--- /dev/null
+++ b/board/freescale/ls1046afrwy/README
@@ -0,0 +1,76 @@
+Overview
+--------
+The LS1046A Freeway Board (iFRWY) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS1046A
+LayerScape Architecture processor. The FRWY-LS1046A provides SW development
+platform for the Freescale LS1046A processor series, with a complete
+debugging environment. The FRWY-LS1046A  is lead-free and RoHS-compliant.
+
+LS1046A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A
+SoC overview.
+
+ FRWY-LS1046A board Overview
+ -----------------------
+ - SERDES1 Connections, 4 lanes supporting:
+      - Lane0: Unused
+      - Lane1: Unused
+      - Lane2: QSGMII
+      - Lane3: Unused
+ - SERDES2 Connections, 4 lanes supporting:
+      - Lane0: Unused
+      - Lane1: PCIe3 with PCIe x1 slot
+      - Lane2: Unused
+      - Lane3: PCIe3 with PCIe x1 slot
+ - DDR Controller
+     - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s
+ -IFC/Local Bus
+    - One 512 MB NAND flash with ECC support
+ - USB 3.0
+    - Two Type A port
+ - SDHC: connects directly to a full microSD slot
+ - QSPI: 64 MB high-speed flash Memory for boot code and storage
+ - 4 I2C controllers
+ - UART
+   - Two 4-pin serial ports at up to 115.2 Kbit/s
+   - Two DB9 D-Type connectors supporting one Serial port each
+ - ARM JTAG support
+
+Memory map from core's view
+----------------------------
+Start Address	 End Address	 Description		Size
+0x00_0000_0000 - 0x00_000F_FFFF  Secure Boot ROM	1MB
+0x00_0100_0000 - 0x00_0FFF_FFFF  CCSRBAR		240MB
+0x00_1000_0000 - 0x00_1000_FFFF  OCRAM0 		64KB
+0x00_1001_0000 - 0x00_1001_FFFF  OCRAM1 		64KB
+0x00_2000_0000 - 0x00_20FF_FFFF  DCSR			16MB
+0x00_7E80_0000 - 0x00_7E80_FFFF  IFC - NAND Flash	64KB
+0x00_7FB0_0000 - 0x00_7FB0_0FFF  IFC - CPLD		4KB
+0x00_8000_0000 - 0x00_FFFF_FFFF  DRAM1			2GB
+0x05_0000_0000 - 0x05_07FF_FFFF  QMAN S/W Portal	128M
+0x05_0800_0000 - 0x05_0FFF_FFFF  BMAN S/W Portal	128M
+0x08_8000_0000 - 0x09_FFFF_FFFF  DRAM2			6GB
+0x40_0000_0000 - 0x47_FFFF_FFFF  PCI Express1		32G
+0x48_0000_0000 - 0x4F_FFFF_FFFF  PCI Express2		32G
+0x50_0000_0000 - 0x57_FFFF_FFFF  PCI Express3		32G
+
+QSPI flash map:
+Start Address    End Address     Description		Size
+0x00_4000_0000 - 0x00_400F_FFFF  RCW + PBI + BL2	1MB
+0x00_4010_0000 - 0x00_404F_FFFF  FIP Image
+				  (Bl31 + BL32(optee.
+				  bin) + Bl33(uboot)
+				  + headers for secure
+				  boot)			4MB
+0x00_4050_0000 - 0x00_405F_FFFF  Boot Firmware Env	1MB
+0x00_4060_0000 - 0x00_408F_FFFF  Secure boot headers	3MB
+0x00_4090_0000 - 0x00_4093_FFFF  FMan ucode		256KB
+0x00_4094_0000 - 0x00_4097_FFFF  QE/uQE firmware	256KB
+0x00_409C_0000 - 0x00_409F_FFFF  Reserved		256KB
+0x00_4100_0000 - 0x00_43FF_FFFF  FIT Image		48MB
+
+Booting Options
+---------------
+a) QSPI boot
+b) microSD boot
diff --git a/board/freescale/ls1046afrwy/ddr.c b/board/freescale/ls1046afrwy/ddr.c
new file mode 100644
index 0000000..daf17e0
--- /dev/null
+++ b/board/freescale/ls1046afrwy/ddr.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int fsl_initdram(void)
+{
+	gd->ram_size = tfa_get_dram_size();
+
+	if (!gd->ram_size)
+		gd->ram_size = fsl_ddr_sdram_size();
+
+	return 0;
+}
diff --git a/board/freescale/ls1046afrwy/eth.c b/board/freescale/ls1046afrwy/eth.c
new file mode 100644
index 0000000..9f8bd92
--- /dev/null
+++ b/board/freescale/ls1046afrwy/eth.c
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <fm_eth.h>
+#include <fsl_dtsec.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+
+#include "../common/fman.h"
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+	struct memac_mdio_info dtsec_mdio_info;
+	struct mii_dev *dev;
+	u32 srds_s1;
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+	srds_s1 = in_be32(&gur->rcwsr[4]) &
+			FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	dtsec_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+
+	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+	/* Register the 1G MDIO bus */
+	fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+	/* QSGMII on lane B, MAC 6/5/10/1 */
+	fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT1_PHY_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT2_PHY_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC10, QSGMII_PORT3_PHY_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT4_PHY_ADDR);
+
+	switch (srds_s1) {
+	case 0x3040:
+		break;
+	default:
+		printf("Invalid SerDes protocol 0x%x for LS1046AFRWY\n",
+		       srds_s1);
+		break;
+	}
+
+	dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+	fm_info_set_mdio(FM1_DTSEC6, dev);
+	fm_info_set_mdio(FM1_DTSEC5, dev);
+	fm_info_set_mdio(FM1_DTSEC10, dev);
+	fm_info_set_mdio(FM1_DTSEC1, dev);
+
+	cpu_eth_init(bis);
+#endif
+
+	return pci_eth_init(bis);
+}
+
+#ifdef CONFIG_FMAN_ENET
+int fdt_update_ethernet_dt(void *blob)
+{
+	u32 srds_s1;
+	int i, prop;
+	int offset, nodeoff;
+	const char *path;
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+	srds_s1 = in_be32(&gur->rcwsr[4]) &
+			FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	/* Cycle through all aliases */
+	for (prop = 0; ; prop++) {
+		const char *name;
+
+		/* FDT might have been edited, recompute the offset */
+		offset = fdt_first_property_offset(blob,
+						   fdt_path_offset(blob,
+								   "/aliases")
+						   );
+		/* Select property number 'prop' */
+		for (i = 0; i < prop; i++)
+			offset = fdt_next_property_offset(blob, offset);
+
+		if (offset < 0)
+			break;
+
+		path = fdt_getprop_by_offset(blob, offset, &name, NULL);
+		nodeoff = fdt_path_offset(blob, path);
+
+		switch (srds_s1) {
+		case 0x3040:
+			if (!strcmp(name, "ethernet1"))
+				fdt_status_disabled(blob, nodeoff);
+			if (!strcmp(name, "ethernet2"))
+				fdt_status_disabled(blob, nodeoff);
+			if (!strcmp(name, "ethernet3"))
+				fdt_status_disabled(blob, nodeoff);
+			if (!strcmp(name, "ethernet6"))
+				fdt_status_disabled(blob, nodeoff);
+		break;
+		default:
+			printf("%s:Invalid SerDes prtcl 0x%x for LS1046AFRWY\n",
+			       __func__, srds_s1);
+		break;
+		}
+	}
+
+	return 0;
+}
+#endif
diff --git a/board/freescale/ls1046afrwy/ls1046afrwy.c b/board/freescale/ls1046afrwy/ls1046afrwy.c
new file mode 100644
index 0000000..41412a7
--- /dev/null
+++ b/board/freescale/ls1046afrwy/ls1046afrwy.c
@@ -0,0 +1,223 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include <hwconfig.h>
+#include <ahci.h>
+#include <mmc.h>
+#include <scsi.h>
+#include <fm_eth.h>
+#include <fsl_csu.h>
+#include <fsl_esdhc.h>
+#include <fsl_sec.h>
+#include <fsl_dspi.h>
+
+#define LS1046A_PORSR1_REG 0x1EE0000
+#define BOOT_SRC_SD        0x20000000
+#define BOOT_SRC_MASK	   0xFF800000
+#define BOARD_REV_GPIO		13
+#define USB2_SEL_MASK	   0x00000100
+
+#define BYTE_SWAP_32(word)  ((((word) & 0xff000000) >> 24) |  \
+(((word) & 0x00ff0000) >>  8) | \
+(((word) & 0x0000ff00) <<  8) | \
+(((word) & 0x000000ff) << 24))
+#define SPI_MCR_REG	0x2100000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int select_i2c_ch_pca9547(u8 ch)
+{
+	int ret;
+
+	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+	if (ret) {
+		puts("PCA: failed to select proper channel\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static inline void demux_select_usb2(void)
+{
+	u32 val;
+	struct ccsr_gpio *pgpio = (void *)(GPIO3_BASE_ADDR);
+
+	val = in_be32(&pgpio->gpdir);
+	val |=  USB2_SEL_MASK;
+	out_be32(&pgpio->gpdir, val);
+
+	val = in_be32(&pgpio->gpdat);
+	val |=  USB2_SEL_MASK;
+	out_be32(&pgpio->gpdat, val);
+}
+
+static inline void set_spi_cs_signal_inactive(void)
+{
+	/* default: all CS signals inactive state is high */
+	uint mcr_val;
+	uint mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK |
+				DSPI_MCR_CRXF | DSPI_MCR_CTXF;
+
+	mcr_val = in_be32(SPI_MCR_REG);
+	mcr_val |= DSPI_MCR_HALT;
+	out_be32(SPI_MCR_REG, mcr_val);
+	out_be32(SPI_MCR_REG, mcr_cfg_val);
+	mcr_val = in_be32(SPI_MCR_REG);
+	mcr_val &= ~DSPI_MCR_HALT;
+	out_be32(SPI_MCR_REG, mcr_val);
+}
+
+int board_early_init_f(void)
+{
+	fsl_lsch2_early_init_f();
+
+	return 0;
+}
+
+static inline uint8_t get_board_version(void)
+{
+	u8 val;
+	struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR);
+
+	val = (in_le32(&pgpio->gpdat) >> BOARD_REV_GPIO) & 0x03;
+
+	return val;
+}
+
+int checkboard(void)
+{
+	static const char *freq[2] = {"100.00MHZ", "100.00MHZ"};
+	u32 boot_src;
+	u8 rev;
+
+	rev = get_board_version();
+	switch (rev) {
+	case 0x00:
+		puts("Board: LS1046AFRWY, Rev: A, boot from ");
+		break;
+	case 0x01:
+		puts("Board: LS1046AFRWY, Rev: B, boot from ");
+		break;
+	default:
+		puts("Board: LS1046AFRWY, Rev: Unknown, boot from ");
+		break;
+	}
+	boot_src = BYTE_SWAP_32(readl(LS1046A_PORSR1_REG));
+
+	if ((boot_src & BOOT_SRC_MASK) == BOOT_SRC_SD)
+		puts("SD\n");
+	else
+		puts("QSPI\n");
+	printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[0], freq[1]);
+
+	return 0;
+}
+
+int board_init(void)
+{
+#ifdef CONFIG_SECURE_BOOT
+	/*
+	 * In case of Secure Boot, the IBR configures the SMMU
+	 * to allow only Secure transactions.
+	 * SMMU must be reset in bypass mode.
+	 * Set the ClientPD bit and Clear the USFCFG Bit
+	 */
+	u32 val;
+val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+	out_le32(SMMU_SCR0, val);
+	val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+	out_le32(SMMU_NSCR0, val);
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+	sec_init();
+#endif
+
+	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+	return 0;
+}
+
+int board_setup_core_volt(u32 vdd)
+{
+	return 0;
+}
+
+void config_board_mux(void)
+{
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+	u32 usb_pwrfault;
+	/*
+	 * USB2 is used, configure mux to USB2_DRVVBUS/USB2_PWRFAULT
+	 * USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA
+	 */
+	out_be32(&scfg->rcwpmuxcr0, 0x3300);
+#ifdef CONFIG_HAS_FSL_IIC3
+	/* IIC3 is used, configure mux to use IIC3_SCL/IIC3/SDA */
+	out_be32(&scfg->rcwpmuxcr0, 0x0000);
+#endif
+	out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
+	usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
+			SCFG_USBPWRFAULT_USB3_SHIFT) |
+			(SCFG_USBPWRFAULT_DEDICATED <<
+			SCFG_USBPWRFAULT_USB2_SHIFT) |
+			(SCFG_USBPWRFAULT_SHARED <<
+			SCFG_USBPWRFAULT_USB1_SHIFT);
+	out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
+#ifndef CONFIG_HAS_FSL_IIC3
+	/*
+	 * LS1046A FRWY board has demultiplexer NX3DV42GU with GPIO3_23 as input
+	 * to select I2C3_USB2_SEL_IO
+	 * I2C3_USB2_SEL = 0: I2C3_SCL/SDA signals are routed to
+	 * I2C3 header (default)
+	 * I2C3_USB2_SEL = 1: USB2_DRVVBUS/PWRFAULT signals are routed to
+	 * USB2 port
+	 * programmed to select USB2 by setting GPIO3_23 output to one
+	 */
+	demux_select_usb2();
+#endif
+#endif
+	set_spi_cs_signal_inactive();
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	config_board_mux();
+	return 0;
+}
+#endif
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	u64 base[CONFIG_NR_DRAM_BANKS];
+	u64 size[CONFIG_NR_DRAM_BANKS];
+
+	/* fixup DT for the two DDR banks */
+	base[0] = gd->bd->bi_dram[0].start;
+	size[0] = gd->bd->bi_dram[0].size;
+	base[1] = gd->bd->bi_dram[1].start;
+	size[1] = gd->bd->bi_dram[1].size;
+
+	fdt_fixup_memory_banks(blob, base, size, 2);
+	ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+	fdt_fixup_fman_ethernet(blob);
+#endif
+
+	fdt_fixup_icid(blob);
+
+	return 0;
+}